1. Technical Field
This invention relates to a thin film transistor substrate and a fabricating method thereof, and more particularly to a thin film transistor substrate and a fabricating method thereof wherein a contact size between an electrode and an active layer can be reduced to provide a small and light panel.
2. Description of the Related Art
Generally, a liquid crystal display (LCD) allows each liquid crystal cell that is arranged on a liquid crystal display panel in a matrix to control the light transmittance in accordance with a video signal, thereby displaying a picture.
In each liquid crystal cell, a thin film transistor (TFT) is used as a switching device for supplying a video signal independently. An active layer of such a TFT employs an amorphous silicon (amorphous-Si) or polycrystalline silicon (poly-Si). Herein, when the poly-Si is used, a driving circuit requiring a high response speed can be built in the liquid crystal display panel because the poly-Si has approximately hundred times faster charge mobility than the amorphous-Si.
FIG. 1 schematically shows a liquid crystal display panel employing a conventional poly-TFT.
Referring to FIG. 1, the liquid crystal display panel includes a picture display part 96, a data driver 92 for driving a data line 4 of the picture display part 96, and a gate driver 94 for driving a gate line 2 of the picture display part 96.
The picture display part 96 has liquid crystal cells LC arranged in a matrix to display a picture. Each of the liquid crystal cells LC includes a TFT 30 connected to the gate line 2 and the data line 4. The TFT 30 charges a video signal from the data line 4 into the liquid crystal cell LC in response to a scanning signal from the gate line 2. In response to the charged video signal, the liquid crystal cell LC reacts a liquid crystal having a dielectric anisotropy to control light transmittance, thereby implementing a gray level.
The gate driver 94 sequentially drives the gate line 2. The data driver 92 applies a video signal to the data line 4 whenever the gate line 2 is driven.
Such a liquid crystal display panel is formed by joining a TFT substrate, provided with the data driver 92 and the gate driver 94 along with the TFT 30 of the liquid crystal cell LC, to a color filter substrate provided with a common electrode and a color filter, etc. with a liquid crystal therebetween.
FIG. 2 is a partial plan view of a picture display part of the TFT substrate included in the liquid crystal display panel shown in FIG. 1, and FIG. 3 is a section view of the TFT substrate taken along section line III-III of FIG. 2.
Referring to FIG. 2 and FIG. 3, the picture display part of the TFT substrate includes a TFT 30 connected to the gate line 2 and the data line 4, and a pixel electrode 22 connected to the TFT 30. The TFT 30 may be formed as an N-type or P-type TFT, but the TFT 30 formed as an N-type only will be described below.
The TFT 30 charges a video signal into the pixel electrode 22. To this end, the TFT 30 includes a gate electrode 6 connected to the gate line 2, a source electrode included in the data line 4, and a drain electrode 10 connected via a pixel contact hole 20 passing through the pixel electrode 22 and the protective film 18. The gate electrode 6 overlaps with a channel area 14C of the active layer 14 provided on a buffer film 16 with having a gate insulating film 12 therebetween. The source electrode and the drain electrode 10 are formed in such a manner to be insulated from the gate electrode 6 with having an interlayer insulating film 26 therebetween. Further, the source electrode and the drain electrode 10 are connected, via a source contact hole 24S and a drain contact hole 24D passing through the interlayer insulating film 26 and the gate insulating film 12, to a source area 14S and a drain area 14D of the active layer 14, which are doped with an n+ impurity, respectively. The active layer may include a lightly doped drain (LDD) area (not shown) doped with an n− impurity between the channel area 14C and the source and drain areas 14S and 14D in order to reduce an off current.
A formation of the contact hole 24 and the electrode 10 on such a poly-TFT substrate will be described with reference to FIG. 4A to FIG. 4C below.
Firstly, referring to FIG. 4A, in the poly-TFT substrate, the buffer film 16 is formed on a lower substrate 1 and then the active layer 14 is formed on the buffer film 16. Further, the gate insulating film 12 is formed at the upper portion of the active layer 14 and then the interlayer insulating film 26 is formed thereon.
The active layer 14 is formed by depositing amorphous-Si on the lower substrate 1 and then crystallizing it by a laser into a poly-Si; and thereafter by patterning it by a photolithography and etching process using a mask.
The gate insulating film 12 is formed by entirely depositing an inorganic insulating material such as SiO2, and the like.
The interlayer insulating film 26 is formed by blanket depositing an inorganic insulating material such as SiO2, and the like on the gate insulating film 12.
Referring to FIG. 4B, the interlayer insulating film 26 and the gate insulating film 12 have a contact hole 24 formed therethrough a photolithography and etching process. More specifically, in the photolithography process, the photo-resist pattern is formed by coating a photo-resist onto the interlayer insulating film 26; and then partially exposing to light by arranging a patterned mask at the upper portion of the photo-resist and developing the photo-resist. Thereafter, the contact hole 24 is formed by dry etching and wet etching. The contact hole 24 formed in this manner has a slope, and a section thereof is formed in a trapezoidal shape.
Referring to FIG. 4C, the electrode 10 is deposited onto the surface of the contact hole 24 using a mask. In this case, the electrode 10 is formed in such a manner to cover the entire surface of the contact hole 24 and the peripheral of the aperture of the interlayer insulating film 26.
In reality, when the contact hole 24 connected to the active layer 14 is designed to have a size of 4 μm, a size of the upper contact hole 24 provided at the aperture on the interlayer insulating film 26 becomes about 7 μm and the width of the electrode 10 becomes 11 μm.
As described above, the conventional electrode 10 has a problem in that, since it is formed in such a manner to cover the whole portion of upper contact hole 24 provided at the aperture of the interlayer insulating film 26, it has a large width. Accordingly, there has been suggested a scheme of maximizing a slope of the contact hole 24 in order to reduce a size of the contact hole 24. However, when a slope of the contact hole 24 is maximized, there is a problem in that an electrode 10a, provided at the periphery of the aperture of the interlayer insulating film 26, and an electrode 10b, provided at the contact hole 24, not connected to each other, as shown in FIG. 5. Also, it is necessary to use a wet etching process for the purpose of protecting the active layer 14 when the contact hole 24 is formed. Thus, the contact hole 24 has a slope that is greater than a desired angle, which causes a problem in maximizing a slope of the contact hole 24. Such a formation of the contact hole fails to satisfy the need for a small size contact hole 24, which is required for a small-dimension and light-weight panel.